DESCRIPTION

· The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with storage register and 3-state outputs.
· It features separate clocks for shift and storage registers, a serial input (DS), and a serial output (Q7S) for cascading.
· Includes an asynchronous reset MR input; LOW on MR resets the shift register.
· Data shifts on LOW-to-HIGH transitions of SHCP and transfers to storage register on LOW-to-HIGH transitions of STCP.
· Outputs are enabled when OE is LOW; HIGH on OE sets outputs to high-impedance OFF-state.
· Qualified to AEC-Q100 (Grade 1) for automotive applications.

FEATURES

· Automotive qualification per AEC-Q100 (Grade 1).
· Operating temperature range: -40°C to +125°C.
· 8-bit serial input and 8-bit serial or parallel output.
· Storage register with 3-state outputs and shift register with direct clear.
· Typical shift out frequency: 100 MHz.
· Complies with JEDEC standard no. 7A.
· Input levels: CMOS for 74HC595-Q100, TTL for 74HCT595-Q100.
· ESD protection: HBM exceeds 2000 V, CDM exceeds 1000 V.
· Available in multiple package options including DHVQFN with Side-Wettable Flanks for AOI.

APPLICATIONS

· Serial-to-parallel data conversion.
· Remote control holding register.