DESCRIPTION

· Monolithic Field Programmable System Level Integrated Circuit (FPSLIC™) combining AT40K SRAM-based FPGA and embedded high-performance RISC AVR® core.

· Integrated with extensive data and instruction SRAM, JTAG ICE, and FPGA configuration access from AVR microcontroller core.

· Designed for low static and dynamic power consumption, ideal for portable and handheld applications.

FEATURES

· AT40K FPGA with 5,000 to 40,000 gates and 2 - 18.4 Kbits of distributed single/dual port FPGA user SRAM.

· High-performance DSP optimized FPGA core cell, dynamically reconfigurable in-system.

· AVR enhanced RISC architecture with 120+ instructions, high-performance hardware multiplier, and C code optimized architecture.

· Up to 36 Kbytes of dynamically allocated instruction and data SRAM, and JTAG interface compliant with IEEE std. 1149.1.

· AVR fixed peripherals include industry-standard 2-wire serial interface, two programmable serial UARTs, and multiple timer/counters.

· Support for FPGA custom peripherals, 16 FPGA supplied internal interrupts, and up to four external interrupts to AVR.

· Multiple oscillator circuits, programmable watchdog timer, and software-selectable clock frequency.

· 3.3V 33 MHz PCI-compliant FPGA I/O, high-performance, low-power 0.35µ CMOS five-layer metal process.

APPLICATIONS

· Ideal for portable and handheld applications due to low power consumption.

· Suitable for DSP-based systems with high-performance hardware multiplier and DSP optimized FPGA core cell.

· Applications requiring extensive on-chip debug support and limited boundary-scan capabilities.

· Systems needing multiple timer/counters, programmable serial UARTs, and industry-standard 2-wire serial interface.

· Designs requiring FPGA custom peripherals and FPGA macro library of custom peripherals.