DESCRIPTION

· Monolithic Field Programmable System Level Integrated Circuit (FPSLIC™) integrating AT40K SRAM-based FPGA with an embedded high-performance RISC AVR® core.

· Combines extensive data and instruction SRAM with JTAG ICE for comprehensive system integration.

· Features 5,000 to 40,000 gates of patented SRAM-based AT40K FPGA with FreeRAM™ technology.

FEATURES

· High-performance DSP optimized FPGA core cell with dynamic in-system reconfigurability.

· Low static and dynamic power consumption, ideal for portable and handheld applications.

· Patented AVR Enhanced RISC architecture with 120+ powerful instructions, most executing in a single clock cycle.

· Up to 36 Kbytes of dynamically allocated instruction and data SRAM.

· JTAG (IEEE std. 1149.1 compliant) interface with extensive on-chip debug support.

· AVR fixed peripherals include industry-standard 2-wire serial interface, two programmable serial UARTs, and multiple timer/counters.

· Support for FPGA custom peripherals with AVR peripheral control and 16 decoded AVR address lines accessible to FPGA.

· Multiple oscillator circuits and a programmable watchdog timer with on-chip oscillator.

· 3.3V 33 MHz PCI-compliant FPGA I/O with high-performance I/O structures.

APPLICATIONS

· Suitable for portable and handheld devices due to low power consumption and compact design.

· Ideal for DSP-based systems with high-performance hardware multiplier and optimized C code architecture.

· Effective in applications requiring extensive on-chip debug and boundary-scan capabilities.

· Versatile for systems needing multiple timer/counters, PWM, and real-time clock functionalities.

· Applicable in environments requiring robust I/O structures and PCI compliance.