DESCRIPTION

· The AT94KAL Series is a monolithic Field Programmable System Level Integrated Circuit (FPSLIC™) combining an SRAM-based AT40K FPGA with an embedded high-performance RISC AVR® core, extensive data and instruction SRAM, and JTAG ICE.

FEATURES

· AT40K FPGA with 5,000 to 40,000 gates and 2 - 18.4 Kbits of distributed single/dual port FPGA user SRAM.
· High-performance DSP optimized FPGA core cell, dynamically reconfigurable in-system.
· Patented AVR enhanced RISC architecture with 120+ powerful instructions, most single clock cycle execution.
· Up to 36 Kbytes of dynamically allocated instruction and data SRAM.
· JTAG (IEEE std. 1149.1 compliant) interface with extensive on-chip debug support.
· AVR fixed peripherals including industry-standard 2-wire serial interface, two programmable serial UARTs, and multiple timer/counters.
· Support for FPGA custom peripherals with 16 decoded AVR address lines directly accessible to FPGA.
· Multiple oscillator circuits, programmable watchdog timer, and software-selectable clock frequency.
· 3.3V 33 MHz PCI-compliant FPGA I/O with 20 mA sink/source high-performance I/O structures.
· High-performance, low-power 0.35µ CMOS five-layer metal process.
· State-of-the-art integrated PC-based software suite including co-verification.

APPLICATIONS

· Ideal for portable and handheld applications due to very low static and dynamic power consumption.
· Suitable for DSP-based systems with high-performance hardware multiplier.
· Applications requiring extensive on-chip debug support and limited boundary-scan capabilities.
· Systems needing multiple programmable serial UARTs and timer/counters.
· Designs requiring FPGA custom peripherals and AVR peripheral control.
· Applications benefiting from multiple oscillator circuits and software-selectable clock frequency.
· Systems requiring high-performance, low-power FPGA I/O structures.