DESCRIPTION

· Monolithic Field Programmable System Level Integrated Circuit (FPSLIC™) integrating AT40K SRAM-based FPGA with an embedded high-performance RISC AVR® core.

· Features extensive data and instruction SRAM, JTAG ICE, and supports 5,000 to 40,000 gates of patented SRAM-based AT40K FPGA with FreeRAM™.

FEATURES

· High-performance DSP optimized FPGA core cell with dynamic in-system reconfigurability.

· Patented AVR Enhanced RISC architecture with 120+ powerful instructions, most single clock cycle execution, and a high-performance hardware multiplier.

· Up to 36 Kbytes of dynamically allocated instruction and data SRAM, with up to 16 Kbytes x 16 internal 15 ns instruction SRAM and up to 16 Kbytes x 8 internal 15 ns data SRAM.

· JTAG (IEEE std. 1149.1 compliant) interface with extensive on-chip debug support and limited boundary-scan capabilities.

· AVR fixed peripherals including industry-standard 2-wire serial interface, two programmable serial UARTs, and multiple timer/counters with PWM.

· Support for FPGA custom peripherals with AVR peripheral control and 16 decoded AVR address lines directly accessible to FPGA.

· Multiple oscillator circuits, programmable watchdog timer, and software-selectable clock frequency.

· Operates at VCC: 3.0V - 3.6V with 3.3V 33 MHz PCI-compliant FPGA I/O and 20 mA sink/source high-performance I/O structures.

· High-performance, low-power 0.35µ CMOS five-layer metal process.

APPLICATIONS

· Ideal for portable and handheld applications due to very low static and dynamic power consumption.

· Suitable for DSP-based systems with its high-performance hardware multiplier and C code optimized architecture.

· Effective in real-time clock applications with its oscillator to timer/counter functionality.

· Versatile in custom peripheral development with FPGA macro library and AVR peripheral control.