DESCRIPTION

· The M74HCT573 is a high-speed CMOS octal latch with 3-state outputs, fabricated using silicon gate C2MOS technology.

· It features an 8-bit D-type latch controlled by a latch enable (LE) and output enable (OE) input.

· When LE is high, Q outputs follow the data input; when LE is low, Q outputs latch the D input data.

· When OE is low, outputs are in normal logic state; when OE is high, outputs are in high impedance state.

· Designed to interface HSC 2MOS systems with TTL and NMOS components, with input protection against static discharge and transient excess voltage.

FEATURES

· High speed: tPD = 21ns (typical) at VCC = 4.5V.

· Low power dissipation: ICC = 4µA (max) at TA = 25°C.

· TTL compatible: VIH = 2V (min), VIL = 0.8V (max).

· Balanced propagation delays: tPLH ≅ tPHL.

· Symmetrical output impedance: |IOH| = IOL = 6mA (min).

· Pin and function compatible with 74 series 573.

APPLICATIONS

· Suitable for bus-organized systems due to its 3-state output configuration.

· Ideal for interfacing HSC 2MOS systems with TTL and NMOS components.