DESCRIPTION

· The MC100EP196 is a programmable delay chip (PDC) designed for clock deskewing and timing adjustment.
· It provides variable delay for differential NECL/PECL input transitions.
· Features a programmable matrix of gates and multiplexers for delay control.
· Includes an FTUNE pin for fine-tuning output delay from 0 to 60 ps.
· Offers a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns.
· Supports cascading multiple PDCs for increased programmable range.

FEATURES

· Maximum frequency > 1.2 GHz typical.
· Programmable range: 0 ns to 10 ns.
· Delay range: 2.4 ns to 12.4 ns.
· 10 ps increments.
· PECL mode operating range: VCC = 3.0 V to 3.6 V with VEE = 0 V.
· NECL mode operating range: VCC = 0 V with VEE = -3.0 V to -3.6 V.
· Open input default state.
· Safety clamp on inputs.
· A logic high on the EN pin will force Q to logic low.
· D[10:0] can accept ECL, LVCMOS, or LVTTL inputs.
· VBB output reference voltage.
· Pb-Free devices.

APPLICATIONS

· Clock deskewing in high-speed digital systems.
· Timing adjustment in communication systems.
· Signal delay control in test and measurement equipment.
· Synchronization in data acquisition systems.
· Delay compensation in high-frequency circuits.