DESCRIPTION

· The SY10/100E195 are programmable delay chips (PDCs) designed for clock de-skewing and timing adjustment.

· They provide variable delay of a differential ECL input transition with a digitally-selectable resolution of approximately 20ps.

· The delay is selected by seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control.

· An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range.

FEATURES

· Up to 2ns delay range.

· Extended 100E VEE range of –4.2V to –5.5V.

· ≈20ps/digital step resolution.

· >1GHz bandwidth.

· On-chip cascade circuitry.

· 75KΩ input pulldown resistor.

· Fully compatible with Motorola MC10E/100E195.

· Available in 28-pin PLCC package.

APPLICATIONS

· Clock de-skewing in high-frequency systems.

· Precision timing adjustment in digital circuits.

· Cascade multiple PDCs for extended delay range in complex timing systems.