DESCRIPTION

· The SY10/100E196 are programmable delay chips (PDCs) designed for precise differential ECL input edge placement.

· The delay section includes a chain of gates and a linear ramp delay adjustment.

· The first two delay elements have modified gates with delays 1.25 and 1.5 times the basic gate delay of approximately 80ps.

· The device delay is selected by seven address inputs D[0:6], latched on-chip by a high signal on the latch enable (LEN) control.

· The FTUNE input accepts an analog voltage for further reducing the 20ps resolution.

· An eighth latched input, D7, is provided for cascading multiple PDCs.

FEATURES

· Up to 2ns delay range.

· Extended 100E VEE range of –4.2V to –5.5V.

· Approximately 20ps digital step resolution.

· Linear input for tighter resolution.

· Greater than 1GHz bandwidth.

· On-chip cascade circuitry.

· 75KΩ input pulldown resistor.

· Fully compatible with Motorola MC10E/100E196.

· Available in 28-pin PLCC package.

APPLICATIONS

· Very accurate differential ECL input edge placement.

· Applications requiring precise delay adjustments.

· Systems needing cascadable programmable delay chips.