DESCRIPTION

· The ispClock 5300S Family is an in-system programmable, zero-delay universal fan-out buffer designed for single-ended applications. It supports a wide range of input/output operations from 8MHz to 267MHz and features low output-to-output skew and low jitter peak-to-peak. The device is available in 48-pin and 64-pin TQFP packages and operates across commercial (0 to 70°C) and industrial (-40 to 85°C) temperature ranges.

FEATURES

· Four operating configurations: zero delay buffer, zero delay and non-zero delay buffer, dual non-zero delay buffer, and non-zero delay buffer with output divider.
· Up to 20 programmable fan-out buffers with programmable single-ended output standards and individual enable controls.
· Fully integrated high-performance PLL with programmable lock detect, three "Power of 2" output dividers, and programmable on-chip loop filter.
· Precision programmable phase adjustment per output with 8 settings and a skew range of up to +/- 5ns.
· Flexible clock reference and external feedback inputs with programmable single-ended or differential input reference standards.
· All inputs and outputs are hot socket compliant with full JTAG boundary scan test in-system programming support.

APPLICATIONS

· Circuit board common clock distribution.
· PLL-based frequency generation.
· High fan-out clock buffer.
· Zero-delay clock buffer.