OMAP-L138 Device Overview

1. Device Information

• Part Number: OMAPL138ZWT
• Package Type: 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
• Body Size: 16 mm x 16 mm
• Ball Pitch: 0.80 mm

2. Applications

• Professional or Private Mobile Radio (PMR)
• Remote Radio Unit (RRU)
• Remote Radio Head (RRH)
• Industrial Automation
• Currency Inspection
• Biometric Identification
• Machine Vision (Low-End)
• Smart Grid Substation Protection
• Industrial Portable Navigation Devices

3. Description

The OMAP-L138 C6000™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

4. Features

• Dual-Core SoC:ARM926EJ-S™ RISC MPU: 375 MHz and 456 MHzC674x Fixed- and Floating-Point VLIW DSP: 375 MHz and 456 MHz
• ARM926EJ-S Core:32- and 16-Bit (Thumb®) InstructionsDSP Instruction ExtensionsSingle-Cycle MACARM Jazelle® TechnologyEmbedded ICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture:16KB of Instruction Cache16KB of Data Cache8KB of RAM (Vector Table)64KB of ROM
• C674x Instruction Set Features:Superset of the C67x+ and C64x+ ISAsUp to 3648 MIPS and 2746 MFLOPSByte-Addressable (8-, 16-, 32-, and 64-Bit Data)8-Bit Overflow ProtectionBit-Field Extract, Set, ClearNormalization, Saturation, Bit-CountingCompact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture:32KB of L1P Program RAM/Cache32KB of L1D Data RAM/Cache256KB of L2 Unified Mapped RAM/CacheFlexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):2 Channel Controllers3 Transfer Controllers64 Independent DMA Channels16 Quick DMA ChannelsProgrammable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core:Load-Store Architecture With Nonaligned Support64 General-Purpose Registers (32-Bit)Six ALU (32- and 40-Bit) Functional UnitsSupports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating PointSupports up to Four SP Additions Per Clock, Four DP Additions Every Two ClocksSupports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per CycleTwo Multiply Functional Units:Mixed-Precision IEEE Floating-Point Multiply Supported up to:2 SP × SP → SP Per Clock2 SP × SP → DP Every Two Clocks2 SP × DP → DP Every Three Clocks2 DP × DP → DP Every Four ClocksFixed-Point Multiply Supports Two 32 × 32 Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex MultiplesInstruction Packing Reduces Code SizeAll Instructions ConditionalHardware Support for Modulo Loop OperationProtected Mode OperationExceptions Support for Error Detection and Program Redirection
• Software Support:TI DSP BIOS™Chip Support Library and DSP Library
• 128KB of RAM Shared Memory
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
• Two External Memory Interfaces:EMIFANOR (8- or 16-Bit-Wide Data)NAND (8- or 16-Bit-Wide Data)16-Bit SDRAM With 128-MB Address SpaceDDR2/Mobile DDR Memory Controller With One of the Following:16-Bit DDR2 SDRAM With 256-MB Address Space16-Bit mDDR SDRAM With 256-MB Address Space
• Three Configurable 16550-Type UART Modules:With Modem Control Signals16-Byte FIFO16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
• Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
• Two Master and Slave Inter-Integrated Circuits (I2C Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem (PRUSS):Two Independent Programmable Real-Time Unit (PRU) Cores32-Bit Load-Store RISC Architecture4KB of Instruction RAM Per Core512 Bytes of Data RAM Per CorePRUSS can be Disabled Through Software to Save PowerRegister 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores
• USB 1.1 OHCI (Host) With Integrated PHY (USB1)
• USB 2.0 OTG Port With Integrated PHY (USB0):USB 2.0 High- and Full-Speed ClientUSB 2.0 High-, Full-, and Low-Speed HostEnd Point 0 (Control)End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):Two Clock Zones and 16 Serial Data PinsSupports TDM, I2S, and Similar FormatsDIT-CapableFIFO Buffers for Transmit and Receive
• Two Multichannel Buffered Serial Ports (McBSPs):Supports TDM, I2S, and Similar FormatsAC97 Audio Codec InterfaceTelecom Interfaces (ST-Bus, H100)128-Channel TDMFIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):IEEE 802.3 CompliantMII Media-Independent InterfaceRMII Reduced Media-Independent InterfaceManagement Data I/O (MDIO) Module
• Video Port Interface (VPIF):Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture ChannelsTwo 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
• Universal Parallel Port (uPP):High-Speed Parallel Interface to FPGAs and Data ConvertersData Width on Both Channels is 8- to 16-Bit InclusiveSingle-Data Rate or Dual-Data Rate TransfersSupports Multiple Interfaces With START, ENABLE, and WAIT Controls
• Serial ATA (SATA) Controller:Supports SATA I (1.5 Gbps) and SATA II (3.0 Gbps)Supports All SATA Power-Management FeaturesHardware-Assisted Native Command Queueing (NCQ) for up to 3