74HC573PW,112 Datasheet Summary

General Description

The 74HC573PW,112 is an 8-bit D-type transparent latch with 3-state outputs. It features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, the device operates in transparent mode, allowing data at the inputs to enter the latches and the latch outputs to change in response to corresponding D-input changes. When LE transitions from HIGH to LOW, the latches store the data present at the inputs a set-up time before the transition. The OE input controls the output state, causing the outputs to enter a high-impedance OFF-state when HIGH, without affecting the state of the latches.

Features and Benefits

• Wide supply voltage range: 2.0 V to 6.0 V.
• Low power dissipation due to CMOS technology.
• High noise immunity.
• Input levels: CMOS level for 74HC573, TTL level for 74HCT573.
• Inputs and outputs are on opposite sides of the package, facilitating easy interface with microprocessors.
• Suitable as input or output ports for microprocessors and microcomputers.
• 3-state non-inverting outputs for bus-oriented applications.
• Common 3-state output enable input.
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
• Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V).
• ESD protection: HBM exceeds 2000 V, CDM exceeds 1000 V.
• Multiple package options available.
• Specified for temperature ranges from -40 °C to +85 °C and -40 °C to +125 °C.

Ordering Information

• Package Type: TSSOP20 (SOT360-1)
• Temperature Range: -40 °C to +125 °C
• Description: Plastic thin shrink small outline package with 20 leads and a body width of 4.4 mm.

Pinning Information

Pin Configuration

• OE (Pin 1): 3-state output enable input (active LOW).
• D0 to D7 (Pins 2 to 9): Data inputs.
• GND (Pin 10): Ground (0 V).
• LE (Pin 11): Latch enable input (active HIGH).
• Q0 to Q7 (Pins 12 to 19): 3-state latch outputs.
• VCC (Pin 20): Supply voltage.

Functional Description

The device operates in different modes based on the control inputs:

• Enable and read register (transparent mode): LE = L, OE = L.
• Latch and read register: LE = H, OE = L.
• Latch register and disable outputs: LE = H, OE = H.

Limiting Values

• Supply voltage (VCC): -0.5 V to +7 V.
• Input clamping current (IIK): ±20 mA.
• Output clamping current (IOK): ±20 mA.
• Output current (IO): ±35 mA.
• Supply current (ICC): +70 mA.
• Ground current (IGND): -70 mA.
• Storage temperature (Tstg): -65 °C to +150 °C.
• Total power dissipation (Ptot): 500 mW (derates linearly with temperature for different packages).

Recommended Operating Conditions

• Supply voltage (VCC): 2.0 V to 6.0 V for 74HC573, 4.5 V to 5.5 V for 74HCT573.
• Input voltage (VI): 0 V to VCC.
• Output voltage (VO): 0 V to VCC.
• Ambient temperature (Tamb): -40 °C to +125 °C.
• Input transition rise and fall rate (Δt/ΔV): 625 ns/V at VCC = 2.0 V, 1.67 ns/V at VCC = 4.5 V, 83 ns/V at VCC = 6.0 V.

Static Characteristics

• HIGH-level input voltage (VIH): 1.5 V to 4.2 V depending on VCC.
• LOW-level input voltage (VIL): 0.5 V to 2.8 V depending on VCC.
• HIGH-level output voltage (VOH): 1.9 V to 5.9 V depending on VCC and output current.
• LOW-level output voltage (VOL): 0 V to 0.4 V depending on VCC and output current.
• Input leakage current (II): ±0.1 μA to ±1.0 μA.
• OFF-state output current (IOZ): ±0.5 μA to ±10.0 μA.
• Supply current (ICC): 8.0 μA to 160 μA.
• Input capacitance (CI): 3.5 pF.

Dynamic Characteristics

• Propagation delay (tpd): 14 ns to 225 ns depending on VCC and load capacitance.
• Enable time (ten): 13 ns to 210 ns depending on VCC and load capacitance.
• Disable time (tdis): 13 ns to 225 ns depending on VCC and load capacitance.
• Transition time (tt): 4 ns to 90 ns depending on VCC and load capacitance.
• Pulse width (tW): 14 ns to 120 ns depending on VCC.
• Set-up time (tsu): 3 ns to 75 ns depending on VCC.
• Hold time (th): 1 ns to 15 ns depending on VCC.
• Power dissipation capacitance (CPD): 26 pF.

Package Outline

• Package Type: TSSOP20 (SOT360-1)
• Dimensions: Body width 4.4 mm, length 6.6 mm, height 1.15 mm.
• Lead count: 20 leads.

Abbreviations

• ANSI: American National Standards Institute
• CDM: Charged Device Model
• CMOS: Complementary Metal Oxide Semiconductor
• DUT: Device Under Test
• ESD: ElectroStatic Discharge
• ESDA: ElectroStatic Discharge Association
• HBM: Human Body Model
• JEDEC: Joint Electron Device Engineering Council
• TTL: Transistor-Transistor Logic

Revision History

• Document ID: 74HC_HCT573
• Release Date: 5 August 2024
• Data Sheet Status: Product data sheet
• Change Notice: ESD specification updated according to the latest JEDEC standard.