DESCRIPTION

· The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

· It features separate clocks for shift and storage registers, a serial input (DS), and a serial output (Q7S) for cascading.

· An asynchronous reset MR input resets the shift register when LOW.

· Data shifts on LOW-to-HIGH transitions of SHCP and transfers to the storage register on LOW-to-HIGH transitions of STCP.

· Outputs are enabled when OE is LOW and assume a high-impedance state when OE is HIGH.

FEATURES

· Wide supply voltage range: 1.0 V to 3.6 V.

· CMOS low power dissipation and direct interface with TTL levels.

· Output ground bounce < 0.8 V and HIGH-level output voltage undershoot > 2 V at VCC = 3.3 V.

· Shift register with direct clear and parallel/serial output capabilities.

· Complies with JEDEC standards and offers ESD protection: HBM > 2000 V, CDM > 1000 V.

· Multiple package options and specified from -40 °C to 125 °C.

APPLICATIONS

· Serial-to-parallel data conversion.

· Remote control holding register.