DESCRIPTION

· The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered D-type flip-flops with 3-state outputs.

· Can be used as two 8-bit flip-flops or one 16-bit flip-flop.

· Features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits.

· Inputs can be driven from either 3.3 V or 5 V devices, suitable for mixed 3.3 V and 5 V environments.

· Schmitt-trigger action at all inputs for tolerance to slower input rise and fall times.

· Fully specified for partial power down applications using IOFF.

FEATURES

· Overvoltage tolerant inputs to 5.5 V.

· Wide supply voltage range from 1.2 V to 3.6 V.

· CMOS low power dissipation.

· Multibyte flow-through standard pinout architecture.

· Low inductance multiple supply pins for minimum noise and ground bounce.

· Direct interface with TTL levels.

· All data inputs have bus hold (74LVCH16374A only).

· High-impedance outputs when VCC = 0 V.

· IOFF circuitry provides partial Power-down mode operation.

· Complies with JEDEC standards: JESD8-7A, JESD8-5A, JESD8-C/JESD36.

· ESD protection: HBM exceeds 2000 V, CDM exceeds 1000 V.

· Specified from -40 °C to +85 °C and -40 °C to +125 °C.

APPLICATIONS

· Suitable for use in mixed 3.3 V and 5 V environments.

· Ideal for applications requiring partial power down mode.

· Used in systems with TTL level interfaces.

· Applicable in environments with potential overvoltage conditions.