A4480KLJTR-T – Automotive 5 V, 50 mA Wide-Input Buck/Boost Linear Regulator

With Output Short-to-Battery Protection & Power-Good Flag

1. Device Identity

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2. Key Features & Benefits

• AEC-Q100 Grade-0 automotive qualified (–40 °C to +150 °C junction)
• 3.5 V – 28 V continuous input, 40 V load-dump survival
• Integrated boost charge-pump maintains 5 V output even when VIN < 5 V
• 50 mA guaranteed load current (derates to ≈ 30 mA at VIN = 3.5 V, see Fig. 3)
• Fold-back short-circuit + short-to-battery protection on VOUT pin (–1 V to 40 V tolerant)
• Under-voltage lock-out (UVLO), over-voltage (OVP), under-voltage (UVP) and thermal shutdown (TSD)
• Power-OK (POK) open-drain flag for microprocessor reset
• High-voltage enable input (ENB) – 40 V tolerant, 100 kΩ internal pull-down
• Pin-to-pin & pin-to-ground tolerant on every pin – robust for truck / 24 V systems
• 35 °C/W RθJA on 4-layer JEDEC board (eSOIC with thermal pad)

3. Applications

• Micro-controller / sensor supply in ECUs
• CAN, LIN, FlexRay transceiver 5 V rails
• Automotive clusters, gateways, camera modules
• 12 V / 24 V truck & bus systems requiring short-to-battery immunity

4. Electrical Characteristics (3.5 V ≤ VIN ≤ 28 V, TJ –40 °C to 150 °C)

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5. Typical Application Circuit

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VIN 13.5 V ── C1 2.2 µF ──┬── Pin 1 VIN
                           │
D1 (24 V zener)*           │
                           │
Enable (IGN) ── R1 100 k ──┴── Pin 5 ENB
                           │
CP1 ─── C2 0.47 µF ─── CP2 (pins 2-3)
                           │
VREG ── C3 2.2 µF ── GND (pins 8-6)
                           │
VOUT ── C4 4.7 µF ── GND (pins 7-6) → 5 V / 50 mA load
                           │
POK ── 100 k pull-up ── µP RESET

Optional diodes D1/D2 only if ENB must survive VIN > 28 V when regulator is off.

6. Pin-out (Top View, eSOIC-8 LJ)

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   VIN   1  o---o  8  VREG
   CP1   2         7  VOUT
   CP2   3         6  GND
   POK   4         5  ENB
   
   Exposed pad on bottom – connect to large GND plane with multiple vias for 35 °C/W rating.

7. Protection & Diagnostics Summary

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8. Packaging & Ordering

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9. Thermal & Layout Notes

• RθJA = 35 °C/W on 4-layer JEDEC board – sufficient for 50 mA at 150 °C ambient with < 0.5 W dissipation.
• Place all capacitors within 3 mm of respective pins; keep ground plane uninterrupted beneath exposed pad.
• Avoid traces under exposed pad – use 0.3 mm thermal vias to inner GND planes.

10. Revision & PCN History

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11. Reference Documents

• A4480 Datasheet Rev. 6 (Sep 2024) – Allegro MicroSystems
• AEC-Q100 qualification report (grade 0) – available under NDA
• Allegro application note “Optimizing Thermal Performance of eSOIC Regulators”