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Allegro MicroSystems A4481KLJTR-T
- Part Number:
A4481KLJTR-T
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RoHS Compliant - Datasheet:
A4481KLJTR-T_Datesheet - Description:
IC REG LINEAR 5V 50MA 8SOIC
- In stock 6,000
A4481KLJTR-T – Complete Datasheet Summary
Automotive 5 V, 50 mA LDO with 50 V Load-Dump & Short-to-Battery Protection
1. Device Overview
- Function: Ultra-rugged 5 V linear regulator for 12 V / 24 V vehicle rails
- Grade: “K” = AEC-Q100 Grade-0 (–40 °C … +150 °C junction)
- Package: 8-pin eSOIC with exposed thermal pad (suffix “LJ”)
- Shipping suffix “TR-T”: 3 000 pcs on 7-inch (330 mm) Ø reel, 12 mm embossed tape
2. Key Features
- Input operating window: 5.25 V … 40 V continuous, survives 50 V load-dump
- Output: 5 V ±1 %, 50 mA max load, 150 mV typical dropout @ 25 mA
- Short-to-battery protection: output pin tolerates +32 V independent of VIN (harness-fault safe)
- Diagnostics: open-drain Power-OK (POK) flag for UV, OV, TSD, ENB-low
- Enable: high-voltage logic pin (ENB) accepts up to 50 V – can be tied directly to battery or µC
- Protection suite:Fold-back current limit (80 mA typ → 23 mA typ when shorted)Thermal shutdown 165 °C (15 °C hysteresis)Input UVLO with 0.2 V hysteresisOutput UV / OV comparators with 15-50 mV hysteresis & 15 µs deglitch
- Pin-to-pin & pin-to-ground tolerant on every pin – no external diode needed
3. Absolute Maximum Ratings
| Parameter | Symbol | Value | Unit |
|---|---|---|---|
| VIN, ENB to GND | – | –0.3 … 50 | V |
| VOUT to GND | – | –0.3 … 32 | V |
| All other pins | – | –0.3 … 7 | V |
| Junction temperature | Tj | –40 … 165 | °C |
| Storage temperature | Tstg | –40 … 150 | °C |
4. Electrical Characteristics (5.25 V ≤ VIN ≤ 40 V, –40 °C ≤ Tj ≤ 150 °C)
| Parameter | Min | Typ | Max | Unit | Condition |
|---|---|---|---|---|---|
| VOUT accuracy | 4.95 | 5.00 | 5.05 | V | IOUT = 25 mA |
| Load regulation | –1 | – | +1 | % | 5 mA ≤ IOUT ≤ 50 mA |
| Line regulation | – | 0.05 | 0.20 | % | VIN = 5.35 … 40 V, 25 mA |
| Quiescent current | – | 3.4 | 5.0 | mA | ENB = high, no load |
| Sleep current | – | 1 | 10 | µA | ENB = low |
| Current limit | –80 | –55 | –140 | mA | VOUT = 5 V |
| Foldback current | –35 | –23 | –13 | mA | VOUT = 0 V |
| POK low voltage | – | 150 | 400 | mV | IPOK = 4 mA |
| POK leakage | – | – | 2 | µA | VPOK = 3.3 V |
5. External Components
- CIN: 2.2 µF/X5R, ≥50 V (100 V if short-to-battery survival required)
- COUT: 3 µF … 10 µF/X5R or X7R, ≥10 V (50 V for off-board sensors)
- Pull-up on POK: 10 kΩ … 100 kΩ to any logic rail ≤ 7 V
6. Thermal Information
| Parameter | Value | Unit |
|---|---|---|
| RθJA (JEDEC 2s2p board) | 35 | °C/W |
| Max power @ 25 °C ambient | 4.0 | W |
| Derating factor | 28.6 | mW/°C PDISS ≈ (VIN – 5 V) × IOUT + VIN × 3.4 mA – use graph in datasheet to de-rate current vs. TA and VIN. |
7. Functional Description
- Enable: ENB high > 2 V starts regulator after 15 µs deglitch; ENB low < 0.8 V shuts down in 15 µs
- POK: high when VOUT within ±10 % of 5 V; pulled low for any fault – open-drain, needs pull-up
- Short-to-battery: if VOUT is forced above 7.2 V, internal disconnect opens; device survives 32 V indefinitely
- Startup time: 0.7 … 2.3 ms into 4.7 µF, 50 mA load
8. Package & PCB Layout (suffix LJ)
- Outline: 8-pin eSOIC, 3.9 mm × 4.9 mm body, 1.27 mm pitch, exposed pad = GND
- Land pattern: follow Allegro DWG-0000380 & IPC-7351 SOIC127P600X175-9AM
- Thermal vias: 0.3 mm diameter, 0.7 mm pitch grid under exposed pad to inner/ bottom copper
- Placement: keep CIN, COUT within 3 mm of pins; route VOUT trace away from high-dV/dT nodes
9. Typical Applications
- 5 V rail for automotive MCUs, CAN/LIN transceivers, sensors
- Keep-alive supply during cranking (UVLO starts ≥ 4.75 V)
- Sensor modules subject to wiring harness faults (short-to-battery)
- Industrial 24 V distributed power (survives 50 V surge)
10. Ordering Information
A4481KLJTR-T
- Temperature: –40 °C … +150 °C (K grade)
- Package: 8-pin eSOIC LJ
- Reel: 3 000 pieces, 7-inch reel, 12 mm tape width, 8 mm pitch
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