AD9912ABCPZ 1 GSPS Direct Digital Synthesizer (DDS) with 14-Bit DAC Specifications

Basic Information

• Part Number: AD9912ABCPZ
• Product Category: Direct Digital Synthesizer (DDS) with Integrated DAC
• Core Function: High-performance frequency synthesis with digital-to-analog conversion
• RoHS Compliance: Yes (denoted by "Z" in part number)
• Operating Temperature Range: -40°C to +85°C (industrial grade)
• Package Type: 64-lead Lead Frame Chip Scale Package (LFCSP), 9 mm × 9 mm body, 0.75 mm height (Package Option: CP-64-22)
• Key Features:

Electrical Specifications

Supply Voltage & Current

System Clock Input

• Modes: PLL Bypassed, PLL Enabled (external signal), Crystal Resonator (PLL Enabled)
• PLL Bypassed Input Range: 250 MHz ~ 1 GHz (differential/single-ended, ac-coupled)
• PLL Enabled Input Range: 25 MHz ~ 200 MHz (with doubler); VCO ranges: Low (700-810 MHz), Auto (810-900 MHz), High (900-1000 MHz)
• Crystal Compatibility: 25 MHz, 3.2 mm × 2.5 mm AT cut (max motional resistance 100 Ω)

DAC Output Characteristics

• Frequency Range (1st Nyquist Zone): 0 MHz ~ 450 MHz
• Output Resistance: 50 Ω (single-ended, internally terminated to AVSS)
• Output Capacitance: 5 pF
• Full-Scale Output Current: 8.6 mA ~ 31.7 mA (10-bit granularity), default 20 mA
• Gain Error: ±10% FS
• Wideband SFDR: -59 dBc ~ -79 dBc (0 MHz ~ 500 MHz)
• Narrow-Band SFDR: -86 dBc ~ -96 dBc (±250 kHz offset)

Clock Output Drivers

HSTL Driver (1.8 V Differential)

• Frequency Range: 20 MHz ~ 725 MHz (up to 622.08 MHz OC-12 rate)
• Differential Output Swing: 1080 mV ~ 1480 mV (static)
• Rise/Fall Time (20%-80%): 115 ps ~ 165 ps (100 Ω load, 2 pF)
• Jitter (12 kHz-20 MHz): 1.5 ps ~ 1.6 ps
• Subharmonic Spur Level: -35 dBc (without correction)

CMOS Driver (1.8 V/3.3 V Single-Ended)

• Frequency Range: <150 MHz
• Output Swing (3.3 V): VOH ≥2.7 V, VOL ≤0.4 V (I OH/I OL=1 mA)
• Output Swing (1.8 V): VOH ≥1.4 V, VOL ≤0.4 V (I OH/I OL=1 mA)
• Rise/Fall Time (20%-80%): 3 ns ~ 4.6 ns (20 pF load)
• Duty Cycle: 45% ~ 65%

Phase Noise (250 MHz Output, HSTL Driver)

• 10 Hz offset: -113 dBc/Hz
• 1 kHz offset: -133 dBc/Hz
• 100 kHz offset: -153 dBc/Hz
• 40 MHz offset: -161 dBc/Hz

Power Dissipation

Mechanical & Thermal Specifications

Package Dimensions (mm)

• Body Size: 9.00 (±0.10) × 9.00 (±0.10)
• Package Height: 0.75
• Exposed Pad Size: 5.21 (±0.15) × 5.21 (±0.15)
• Lead Diameter: 0.18 ~ 0.30
• Coplanarity: 0.08 max

Thermal Resistance (Typical, 64-lead LFCSP)

• θJA (Junction-to-Ambient): 25.2 °C/W (still air)
• θJB (Junction-to-Board): 13.9 °C/W (moving air)
• θJC (Junction-to-Case): 1.7 °C/W
• Note: Exposed pad must be soldered to ground for specified thermal performance.

Key Functional Blocks

Direct Digital Synthesizer (DDS)

• FTW Resolution: 48-bit, f_DDS = (FTW / 2⁴⁸) × fₛ
• Phase Control: 14-bit programmable phase offset (ΔΦ = 2π × Δphase / 2¹⁴)
• Power-Up Default Frequencies: 16 preprogrammed options (38.88 MHz ~ 155.52 MHz) via S1-S4 pins

Spur Reduction (SpurKiller)

• 2 independent channels (Spur A/B) for 2nd ~ 15th harmonic reduction
• 8-bit amplitude control + gain ×2 option; 9-bit phase control (±π)
• Typical performance improvement: 6 dB ~ 8 dB (common settings); up to 30 dB (manual tuning)

Serial Control Port

• Interface: 3-wire (default, SDIO) or 4-wire (SDO active)
• Instruction Word: 16-bit (R/W, transfer length, 13-bit address)
• Transfer Modes: MSB-first (default) or LSB-first; streaming mode supported
• Key Pins: SCLK (Pin 64), SDIO (Pin 63), SDO (Pin 62), CSB (Pin 61, active low)

CMOS Output Divider (S-Divider)

• Divide Ratio: 1 ~ 65,535 (base) or 2 ~ 131,070 (with /2 prescaler)
• Trigger Edge: Programmable rising/falling edge
• Required Setting: S-divider/2 bit (Register 0x0106, Bit 0) for FDBK_IN > 400 MHz

Pin Configuration (Key Pins)

Applications

• Agile LO frequency synthesis
• Low-jitter, fine-tune clock generation
• Test and measurement equipment
• Wireless base stations and controllers
• Secure communications
• Fast frequency hopping