ADSP‑21489BSWZ‑4A Complete Technical Summary

1. Basic Identification

2. Core Performance & Benchmarks

• Peak Floating‑Point Performance: 2.4 GFLOPS @ 400 MHz
• 1024‑Point Complex FFT (Radix‑4): 23 μs
• FIR Filter (per tap): 1.25 ns
• IIR Filter (per biquad): 5 ns
• [3×3] × [3×1] Matrix Multiply: 11.25 ns
• Divide (y/x): 7.5 ns
• Inverse Square Root: 11.25 ns

3. Memory Architecture

3.1 Internal Memory

• SRAM: 5 Mbits (4 blocks, single‑cycle access)
• Organization: Supports 16‑/32‑/48‑/64‑bit word access
• ROM: Not populated
• Security: ROM‑based code protection (optional)

3.2 External Memory Interface

• Asynchronous Memory Interface (AMI) only (SDRAM controller disabled in 100‑lead package)
• Supports SRAM, Flash, EPROM
• 4 external banks with independent timing
• 16‑bit data path

4. Key Peripherals

4.1 Audio‑Centric Peripherals

• 8× Serial Ports (SPORTs): I²S, TDM, left/right justified
• S/PDIF Transceiver: Tx/Rx with biphase encoding
• 4× ASRC: Asynchronous Sample Rate Converters, up to −128 dB SNR
• DAI (Digital Applications Interface): Flexible SRU routing
• IDP/PDAP: Input Data Port / Parallel Data Acquisition Port
• 4× Precision Clock Generators (PCG)

4.2 System Peripherals

• 2× SPI, 1× UART, 1× TWI (I²C)
• 3× PWM Units (100‑lead package)
• 2× General‑Purpose Timers + Core Timer
• Watchdog Timer (not available in 100‑lead package)
• Thermal Diode: On‑die temperature monitoring
• JTAG / Emulation: IEEE 1149.1 Test Access Port

4.3 Hardware Accelerators

• FFT, FIR, IIR hardware accelerators
• MTM (Memory‑to‑Memory) DMA
• Up to 65 DMA channels (scatter/gather, delay line)

5. Electrical Specifications

6. Package & Thermal Data

• Package: 100‑Lead LQFP_EP, 16 mm × 16 mm
• Exposed Pad: Must be soldered to GND plane
• θJA (junction‑to‑ambient): 17.8 °C/W (0 m/s)
• θJC (junction‑to‑case): 2.4 °C/W
• ΨJT (junction‑to‑top): 0.24 °C/W
• Lead Pitch: 0.5 mm
• Mounting: Surface Mount

7. Pin & Boot Features

• Pin Count: 100 (LQFP_EP)
• Boot Modes (BOOT_CFG[1:0]):
• Clock Configuration: CLK_CFG[1:0] sets core clock ratio
• I/O Count: ~70 digital I/O via DAI/DPI

8. Key Features

• Full code compatibility with entire SHARC family
• VISA (Variable Instruction Set Architecture): 16/32/48‑bit
• Single‑cycle fetch: 1 instruction + 4 operands
• Hardware zero‑overhead circular buffers
• Fast context switch via secondary registers
• Automotive‑qualified variants available
• Optimized for high‑performance audio processing

9. Typical Applications

• Automotive infotainment & premium audio
• Professional audio systems & AV receivers
• Industrial audio processing & instrumentation
• Medical devices & communications
• Home theater & multi‑channel audio

10. Ordering & Packaging

• Part Number: ADSP‑21489BSWZ‑4A
• Speed Grade: 400 MHz
• RAM: 5 Mbits
• Temperature: −40°C to +125°C
• Package: 100‑LQFP_EP
• RoHS: Yes
• Packaging: Tray / Tape‑and‑Reel