EP900DM/B Classic EPLD Specification Sheet

1. General Description

The EP900DM/B belongs to Altera’s Classic EPLD (Erasable Programmable Logic Device) family, manufactured by Rochester Electronics. It is designed for high-speed, low-power logic integration, leveraging advanced CMOS technology to support 100% TTL emulation. This device integrates multiple PAL- and GAL-type logic functions, offering a balance of logic density, speed, and flexibility for industrial, military, and space-grade applications. It features non-volatile EPROM configuration elements, enabling erasure and reprogramming, and supports a wide range of packages for versatile system integration.

2. Key Features

• Logic Density: Estimated 450 usable gates (aligning with the EP910 variant in the Classic family)
• Macrocells: 24 programmable macrocells, configurable for sequential (D, T, JK, SR flipflops) or combinatorial operation
• I/O Capabilities: Up to 38 maximum user I/O pins, with programmable I/O architecture
• Performance:
• Programmability:
• Clock Flexibility: Dual global clock pins (CLK1, CLK2) and array clock capability for independent register clocking
• Software & Hardware Support: Compatible with Altera MAX+PLUS II development system; programmable via Altera MPU, Data I/O, and third-party programmers
• Quality & Reliability:

3. Package Information

• Package Types: Compatible with the Classic family’s EP910 variant packages, including:
• Lead Finish: RoHS-compliant (Pb-free) options available (per Rochester’s manufacturing standards)
• Temperature Range: Industrial (-40°C to 85°C) and commercial (0°C to 70°C) grades supported
• Storage Temperature: -65°C to 150°C (no bias)

4. Functional Architecture

4.1 Core Components

• Macrocells: 24 macrocells, each with 8 product terms (programmable-AND/fixed-OR structure) and an XOR gate for polarity control. Supports asynchronous clear via a dedicated product term.
• Programmable Registers: Individually configurable as D, T, JK, or SR flipflops, or bypassed for combinatorial logic. Automatically cleared on power-up.
• Clock & Output Control: Two operating modes for output enable/clock select:
• Feedback Select: Global feedback configuration (similar to EP910), allowing macrocell outputs or I/O pin inputs to feed back to the AND array, accessible to all macrocells.

4.2 Block Diagram Overview

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[Dedicated Inputs / I/O Pins] → [Global Bus (True/Complement Signals)] → [Programmable-AND Array] → [OR Gate] → [XOR Gate] → [Programmable Register / Combinatorial Path] → [Tri-State Output Buffer] → [I/O Pins]
                                                                 ↑                                  ↑
                                                         [Feedback Multiplexer]                [Clock/Output Enable Select]
                                                                 ↑                                  ↑
                                                         [Macrocell/I/O Feedback]             [Global Clock / Array Clock]

5. Electrical Characteristics

5.1 Absolute Maximum Ratings

5.2 Recommended Operating Conditions

5.3 DC Electrical Characteristics (VCC = 5V ±5%, TA = 25°C)

5.4 Supply Current (ICC)

5.5 Capacitance (TA = 25°C, f = 1 MHz)

6. Timing Parameters (Turbo Mode Enabled)

6.1 External Timing Parameters (EP910I-12 Variant Reference)

6.2 Internal Timing Parameters (EP910I-12 Variant Reference)

7. Programming & Design Support

7.1 Programming

• Erasure: UV light erasure (windowed ceramic packages) for design modifications.
• Programming Tools: Altera Master Programming Unit (MPU), Data I/O, BP Microsystems, and third-party programmers.
• Security: Programmable security bit to prevent design copying; reset only via UV erasure.

7.2 Software Support

• Development System: Altera MAX+PLUS II (runs on Windows PCs, Sun SPARCstation, HP 9000, IBM RISC System/6000).
• Design Entry: Schematic, VHDL, Verilog HDL, AHDL, EDIF, and LPM interfaces.
• Simulation & Timing: Integrated timing analysis, simulation, and point-to-point delay prediction.