ISL1532IVEZ – Complete Technical Summary
(Extracted from Renesas / Intersil Datasheet FN6173.4 – May 2015)

1. Device Overview1.1 Base Device: ISL1532 – Dual-Channel Differential DSL Line Driver1.2 Package Variant: IVEZ = 20-lead thermally-enhanced HTSSOP (heat-sink TSSOP)1.3 Status: “Not Recommended for New Designs” – official replacement is ISL15331.4 Process: HS30 Bipolar SOI for low power and high voltage capability1.5 RohS: Fully Pb-free, matte-tin termination, MSL-3 @ 260 °C peak reflow
2. Pin-Compatible Upgrade Path• Drop-in replacement for EL1528; integrates 50 kΩ pull-ups on C0/C1 pins and improved slew rate / swing.
3. Key Features• 450 mA peak output current per channel (class-AB output stage)• 44.4 Vp-p differential swing into 100 Ω load (±12 V supplies)• MTPR > 70 dB (26 kHz – 1.1 MHz, 20.4 dBm line power)• Channel separation –80 dB @ 500 kHz• Software / resistor programmable supply current (Full, ¾, ½, Power-down)• Single or split-supply operation (+5 V to ±15 V)
4. Absolute Maximum Ratings (TA = 25 °C)4.1 Supply Voltage (VS+ to VS–): 30 V4.2 Input Voltages: VS– –0.3 V ≤ VIN ≤ VS+ +0.3 V4.3 C0/C1 Pin Voltage: –0.3 V to +6 V4.4 IADJ Pin Voltage: –0.3 V to +4 V4.5 ESD Rating: 3 kV HBM (MIL-3015.7), 250 V MM (EIAJ C-111)4.6 Junction Temperature: +150 °C4.7 Storage Temperature: –65 °C to +150 °C
5. Electrical Characteristics @ ±12 V, 25 °C (per amplifier)5.1 Quiescent Current (Full-Is):IS+ 4.9 mA typ / 6.5 mA maxIS– –4.7 mA typ / –3.5 mA min5.2 Power-Down Current: < 1 mA total5.3 Input Offset Voltage: ±1 mV typ, ±10 mV max5.4 Input Bias Current: ±14 µA max5.5 Trans-impedance (open-loop): 3.4 MΩ typ5.6 Input Voltage Noise: 3.5 nV/√Hz typ5.7 Input Current Noise: 2 pA/√Hz typ
6. AC / Line-Drive Performance6.1 –3 dB Bandwidth: 90 MHz typ (AV = +5, RF = 3 kΩ, RL-diff = 100 Ω)6.2 Slew Rate: 400 V/µs typ (single-ended, 16 V step)6.3 HD2/HD3: –85 dBc / –65 dBc (1 MHz, 2 Vp-p diff, 100 Ω)6.4 Output Impedance: < 0.2 Ω up to 1 MHz
7. Power-Mode Logic (C1, C0 – internal pull-high)C1 C0 | Mode | Supply Current0 0 | Full Is | 100 %0 1 | ¾ Is | ≈ 75 %1 0 | ½ Is | ≈ 50 %1 1 | Power-down | < 1 mA
8. Thermal Information for 20-Ld HTSSOP (IVEZ)8.1 Junction-to-Ambient θJA:35 °C/W (high-conductivity 4-layer PCB, 2 oz Cu, 4 in²)125 °C/W (low-conductivity 2-layer PCB, 1 in²)8.2 Maximum Allowed Pdiss (TA = 85 °C):1.86 W (high-conductivity)0.52 W (low-conductivity)
9. Pinout (20-Ld HTSSOP) – see datasheet fig. for exact pad coordinates1 VINA– 11 VS+2 VINB+ 12 VOUTD3 C0AB 13 VIND–4 C1AB 14 VINC–5 GND 15 VOUTC6 IADJ 16 VOUTB7 VINC+ 17 VINB–8 VIND+ 18 VINA–9 C1CD 19 VOUTA10 C0CD 20 VS–(Exposed thermal pad on underside – connect to solid GND plane.)
10. Typical Application Circuit• Differential ADSL2+ CO line driver with 1:1 transformer, active or passive back-termination, 20 dBm line power, crest factor 5.3.• Component values: RF = 3 kΩ, RG = 750 Ω (AV = 5), RBM = 100 Ω, RP = 15 kΩ (if active termination), 0.22 µF isolation capacitors.
11. PCB Layout Guidelines• Use 4-layer board with internal ground plane; connect exposed pad to GND with array of 13-mil vias.• Place 2.2 µF tantalum + 0.1 µF ceramic bypass on VS+ and VS– within 5 mm of package.• Keep feedback and gain resistor pads < 2 mm from inverting input to minimise parasitic capacitance.• Do not route ground plane beneath input pins to avoid common-mode peaking.
12. Ordering Information (RoHS-compliant, Pb-free)ISL1532IVEZ – 20 Ld HTSSOP, –40 °C to +85 °C, tubeISL1532IVEZ-T7 – 20 Ld HTSSOP, 7″ reel (500 pcs)ISL1532IVEZ-T13 – 20 Ld HTSSOP, 13″ reel (2 500 pcs)ISL1532IVEZ-EVAL – Demonstration board available
13. Handling & Reliability• MSL-3 moisture sensitivity; bake before use if exceeded floor life.• ESD Class 0B – handle in static-controlled workstation.• Reflow profile: IPC/JEDEC J-STD-020, peak 260 °C (see TB493).