DESCRIPTION

· The LMK03318 is an ultra-low-noise PLL clock generator with a fractional-N frequency synthesizer, integrated VCO, and flexible clock distribution.

· It supports pin-selectable configuration states stored in on-chip EEPROM, reducing BOM cost and board area by replacing multiple oscillators and clock distribution devices.

· The device is designed to generate multiple clocks for various multi-gigabit serial interfaces and digital devices, improving reliability and reducing bit-error rate (BER) in high-speed serial links.

FEATURES

· Ultra-low noise and high performance with jitter as low as 100-fs RMS typical for FOUT > 100 MHz.

· Flexible device options including up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL, or LVCMOS outputs, or any combination.

· Dual inputs with automatic or manual selection, supporting crystal input from 10 to 52 MHz and external input from 1 to 300 MHz.

· Frequency margining options include fine frequency margining using a low-cost pullable crystal reference and glitchless coarse frequency margining using output dividers.

· Operates with a 3.3-V core and 1.8-V, 2.5-V, or 3.3-V output supply, suitable for industrial temperature ranges from -40ºC to 85ºC.

APPLICATIONS

· Switches and routers, network and telecom line cards, servers, and storage systems.

· Wireless base stations, PCIe Gen1, Gen2, Gen3, Gen4, test and measurement equipment, and broadcast infrastructure.