DESCRIPTION

· The LMK61E2 is an ultra-low jitter PLLatinum™ programmable oscillator with a fractional-N frequency synthesizer and integrated VCO, designed to generate commonly used reference clocks.

· Outputs can be configured as LVPECL, LVDS, or HCSL, supporting frequencies up to 1GHz, 900MHz, and 400MHz respectively.

· Features self start-up from on-chip EEPROM, factory programmed to generate a 156.25-MHz LVPECL output.

· Device registers and EEPROM settings are fully programmable in-system through an I2C serial interface.

· Operates from a single 3.3-V ±5% supply, with internal power conditioning for excellent power supply ripple rejection (PSRR).

· Provides fine and coarse frequency margining options through I2C interface for system design verification tests (DVT).

FEATURES

· Ultra-Low Noise, High Performance: Jitter of 90fs RMS typical for fOUT > 100MHz, PSRR of -70dBc for robust supply noise immunity.

· Flexible Output Format: User selectable LVPECL up to 1GHz, LVDS up to 900MHz, HCSL up to 400MHz.

· Total Frequency Tolerance: ±50ppm.

· System Level Features: Frequency margining (fine and coarse), internal EEPROM for user configurable default settings.

· Other Features: Device control via I2C, 3.3-V operating voltage, industrial temperature range (-40ºC to +85ºC), 7-mm × 5-mm 8-pin package.

APPLICATIONS

· High-Performance Replacement for Crystal-, SAW-, or Silicon-Based Oscillators.

· Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN.

· Test and Measurement.

· Medical Imaging.

· FPGA, Processor Attach.