DESCRIPTION

· The MC10E/100E196 is a programmable delay chip (PDC) designed for precise differential ECL input edge placement.

· It features a chain of gates and a linear ramp delay adjust for accurate delay control.

· The delay resolution is approximately 20 ps, selectable via seven address inputs D[0:6].

· The FTUNE input allows for finer resolution adjustment, distinguishing it from the E195.

· An eighth input, D7, enables cascading multiple PDCs for extended programmable range.

· The VBB pin provides a reference voltage for single-ended input conditions.

FEATURES

· 2.0 ns worst-case delay range with ≈20 ps/delay step resolution.

· Linear input for tighter resolution and >1.0 GHz bandwidth.

· On-chip cascade circuitry for controlling multiple PDCs.

· PECL mode operating range: VCC = 4.2 V to 5.7 V with VEE = 0 V.

· NECL mode operating range: VCC = 0 V with VEE = -4.2 V to -5.7 V.

· Internal 50 kΩ pulldown resistors and ESD protection.

· Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.

APPLICATIONS

· Precision timing and delay applications in high-speed digital systems.

· Signal synchronization and edge placement in ECL-based circuits.

· Systems requiring cascadable delay elements for extended range.

· Applications needing temperature-compensated delay control.

· High-frequency signal processing with tight resolution requirements.