DESCRIPTION

· The MC100EP195B is a Programmable Delay Chip (PDC) designed for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition with a resolution of about 10 ps and a net range of up to 10.2 ns. The delay is selected by 10 data select inputs D[9:0] and controlled by the LEN pin. The IN/IN inputs accept LVPECL, LVDS level signals, and the device has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for cascading multiple PDCs for increased programmable range.

FEATURES

· Maximum Input Clock Frequency >1.2 GHz

· Programmable Range: 0 ns to 10 ns

· Delay Range: 2.2 ns to 12.2 ns

· 10 ps Increments

· PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V

· NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V

· IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels

· A Logic High on the EN Pin Will Force Q to Logic Low

· D[10:0] Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels

· Pb-Free Devices

· VBB Output Reference Voltage

APPLICATIONS

· Clock Deskewing

· Timing Adjustment

· Signal Delay Control

· High-Speed Data Processing

· Precision Timing Systems