DESCRIPTION

· The MC100EP196B is a Programmable Delay Chip (PDC) designed for clock deskewing and timing adjustment.
· It provides variable delay for differential NECL/PECL input transitions with a tunable range using the FTUNE pin.
· The delay section includes a programmable matrix of gates and multiplexers, offering a digitally selectable resolution of about 10 ps and a net range up to 10.4 ns.
· The device features a fixed minimum delay of 2.2 ns and supports cascading multiple PDCs for extended programmable range.

FEATURES

· Maximum Input Clock Frequency >1.2 GHz Typical.
· Programmable Range: 0 ns to 10 ns with Delay Range: 2.2 ns to 12.4 ns.
· 10 ps Increments with Linearity ±40 ps max.
· Operates in PECL Mode: VCC = 3.0 V to 3.6 V with VEE = 0 V, and in NECL Mode: VCC = 0 V with VEE = −3.0 V to −3.6 V.
· IN/IN Inputs accept LVPECL, LVNECL, LVDS Levels.
· D[10:0] can select LVPECL, LVCMOS, or LVTTL Input Levels.
· Includes VBB Output Reference Voltage and is Pb-Free.

APPLICATIONS

· Ideal for applications requiring precise clock deskewing and timing adjustments.
· Suitable for systems utilizing LVPECL, LVNECL, or LVDS level signals.
· Can be used in cascaded configurations for enhanced delay programmability.