DESCRIPTION

· The SN54LS137 and SN74LS137 are 3-line to 8-line decoders/demultiplexers with address latches.

· These devices are designed to decode three binary address inputs into one of eight mutually exclusive outputs.

· They feature an enable input for cascading and an address latch for holding the input data.

FEATURES

· 3-to-8 line decoding/demultiplexing with address latches.

· Active low mutually exclusive outputs.

· Enable input for cascading multiple devices.

· Wide operating voltage range: 4.75V to 5.25V.

· Low power consumption: 32mW typical.

APPLICATIONS

· Memory address decoding in microprocessor systems.

· Data routing in multiplexed systems.

· Code conversion and demultiplexing in digital circuits.

· General-purpose logic functions in various electronic systems.