X9420WV14IZ-2.7 – Comprehensive Datasheet Extract
(Organized by topic, English only, title-cased headings)

1. Device Identity• Full part number: X9420WV14IZ-2.7• Family: X9420 low-noise, low-power, SPI-bus XDCP™ digitally-controlled potentiometer• Manufacturer: Renesas (formerly Intersil)• Revision / date: FN8195 Rev. 1.00, 26-Apr-2006• Status: “Not recommended for new designs” – suggested substitutes ISL22416, ISL22419, ISL95311, ISL95711• Package: 14-lead TSSOP, 4.4 mm body (JEDEC MO-153)• Lead finish: Pb-free plus anneal (matte Sn), RoHS-compliant, MSL-3• Top marking: “X9420 WZI” + date/lot code
2. Ordering Options Encapsulated in WV14IZ-2.7• Resistance value: 10 kΩ ±20 % (end-to-end)• Temperature grade: Industrial, –40 °C to +85 °C (suffix “I”)• Supply range: 2.7 V – 5.5 V (suffix “-2.7”)• Tape & reel: 2 k pcs / 13-in reel, 8 mm carrier, 0.65 mm pitch
3. Key Features• Single solid-state potentiometer, 64 taps (6-bit)• Four non-volatile data registers (DR0–DR3) plus volatile wiper counter register (WCR)• SPI serial interface up to 2 MHz; 2-wire mode possible (SI/SO tied)• Power-on recall from DR0 to WCR• Direct R/W, register-to-wiper transfer, increment/decrement commands• Low noise: –140 dBV @ 1 kHz• Standby current: 1 µA max• Endurance: 100 k EEPROM writes per bit, 100-year data retention• Analog supplies bipolar: V+ = +2.7 V…+5.5 V, V– = –2.7 V…–5.5 V, (V+)–(V–) ≤ 12 V• Digital supply: VCC = 2.7 V – 5.5 V
4. Absolute Maximum Ratings• Voltage on SCK, SI, CS, A0, WP, HOLD: –1 V to +7 V• V+ vs VSS: +10 V• V– vs VSS: –10 V• (V+) – (V–): 12 V max• Potentiometer terminals (VH, VL, VW): V– to V+• Any terminal current: ±6 mA• Tj: 150 °C• Storage: –65 °C to +150 °C• Lead soldering: 300 °C / 10 s
5. Recommended Operating Conditions• Ambient: –40 °C to +85 °C (industrial grade)• VCC: 2.7 V – 5.5 V• V+: +2.7 V – +5.5 V• V–: –2.7 V – –5.5 V• (V+) – (V–): ≥ 5 V, ≤ 12 V• Power-up sequence: VCC first, then V+/V–, then potentiometer pins; ramp rate 0.2 – 50 V/ms
6. Analog Specifications (typ @ 25 °C, V+/V– = ±5 V unless noted)• End-to-end resistance: 10 kΩ ±20 %• Wiper resistance: 40 Ω (±5 V), 100 Ω (±3 V) @ 1 mA• Resolution: 1.6 % (64 steps)• Absolute linearity: ±1 MI (MI = RTOT/63)• Relative linearity: ±0.2 MI• Temp-co RTOTAL: ±300 ppm/°C• Ratiometric temp-co: ±20 ppm/°C• Noise: –140 dBV/√Hz @ 1 kHz• Terminal leakage: 0.1 µA typ, 10 µA max (stand-by)• Capacitances: CH/CL/CW = 10 pF / 10 pF / 25 pF
7. Digital / DC Characteristics• VIH: 0.7 VCC to VCC + 0.5 V• VIL: –0.5 V to 0.1 VCC• VOL: 0.4 V max @ 3 mA• ICC active: 400 µA typ (2 MHz, SO open)• ICC write: 1 mA typ (EEPROM store)• ISB: 1 µA max (stand-by)• Input leakage: ±10 µA• Output leakage: ±10 µA
8. AC & Timing Limits (VCC = 5 V, CL = 100 pF)• fSCK max: 2 MHz• tCYC: 500 ns min• tSU/tH: 50 ns setup / hold• tV (SO valid): 100 ns max• tDIS (SO disable): 500 ns max• HOLD setup/hold: 100 ns• tWR (EEPROM store): 5 ms typ, 10 ms max• tWRL (wiper load): 10 µs max• tWRID (increment step): 450 ns max
9. Instruction Set Summary• 8 commands: read/write WCR, read/write DR, XFR DR↔WCR, Increment/Decrement, Read Status (WIP)• Address byte: 0101 110A0 (A0 = pin state)• All EEPROM writes self-timed; poll WIP bit to check completion
10. Typical Application Circuits• 3-terminal potentiometer: variable voltage divider, offset trim, sensor calibration• 2-terminal rheostat: variable gain, current set, filter tuning• Cascaded for stereo/channel matching, dual-supply op-amp offset nulling• Buffered reference: rail-to-rail output using low-noise op-amp• Power-supply sequencing enforced to avoid wiper memory corruption
11. Package & Mechanical Data (TSSOP-14)• Body: 4.4 × 5.0 × 1.1 mm max• Lead pitch: 0.65 mm• Pin-1 chamfer or dot index• Moisture sensitivity: MSL-3, 260 °C peak reflow• Packing: 2 k pcs / 13-in reel, anti-static dry-pack
12. Design & Layout Hints• Place 0.1 µF + 1 µF ceramic close to VCC pin; separate analog/digital grounds, star-connect at VSS• Keep digital traces away from VH/VL/VW to minimize crosstalk• Use 100 Ω series on digital lines if long cables (>20 cm)• Do not apply voltages to potentiometer pins before V+/V– are present• Allow 5 ms after power-up before first write; poll WIP = 0 before next EEPROM command• For lowest noise, buffer wiper with low-input-bias op-amp (e.g., OPA376, ISL28134)
13. Endurance & Data Retention• 100 k write cycles per EEPROM bit minimum• 100-year data retention @ 25 °C (industry standard EEPROM extrapolation)• No wear-leveling needed; DR0–DR3 can be rotated for higher effective endurance
14. Obsolescence / Migration• Renesas status: NRND (Not Recommended for New Designs)• Pin-compatible upgrades: ISL22416 (single, 128-tap), ISL22419 (dual), ISL95311/95711 (lower noise, I²C)• Last-time-buy date: consult Renesas PCN portal; typical 5-year window after NRND
15. Related Documentation & Tools• Datasheet: FN8195 Rev. 1.00 (26-Apr-2006)• SPICE & IBIS models: available on Renesas web (ISL22416 family)• Evaluation board: ISL22416EV1Z (drop-in for X9420WV14 footprint)