DESCRIPTION

· The AD9512 is a clock distribution IC designed for low jitter and low phase noise applications, providing five independent clock outputs.

· It features two 1.6 GHz differential clock inputs and five programmable dividers, each capable of dividing by any integer up to 32.

· Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.

· One LVDS/CMOS output includes a programmable delay element with up to 10 ns of delay, offering fine-tuning with 5-bit resolution.

· The device is controlled via a serial control port and is available in a space-saving 48-lead LFCSP package.

FEATURES

· Two 1.6 GHz differential clock inputs

· Five programmable dividers (1 to 32)

· Phase select for output-to-output coarse delay adjustment

· Three independent 1.2 GHz LVPECL outputs with additive output jitter of 225 fs rms

· Two independent LVDS (800 MHz) or CMOS (250 MHz) clock outputs with additive output jitter of 275 fs rms

· Fine delay adjust on one LVDS/CMOS output

· Serial control port

· Space-saving 48-lead LFCSP package

APPLICATIONS

· Low jitter, low phase noise clock distribution

· Clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

· High-performance wireless transceivers

· High-performance instrumentation

· Broadband infrastructure