CY27410LTXI-025
4-PLL Spread-Spectrum Clock Generator, 48-pin QFN, Industrial Temperature, Factory-Pre-Programmed
Infineon (formerly Cypress)

1. Ordering & Identity• Full part number: CY27410LTXI-025• Family: CY27410 – 4-PLL jitter-attenuating clock generator• Package: LT = 48-pin QFN (7 mm × 7 mm × 1.0 mm, 0.5 mm pitch)• Temperature grade: I = Industrial –40 °C to +85 °C• Configuration: Blank field = factory pre-programmed (025 is the customer-specific code for the embedded frequency table / pin-out)• Shipping: Tube (standard); add “T” suffix (CY27410LTXI-025T) for 13-inch tape-and-reel
2. Core Function• 4 independent fractional-N PLLs (0 ppm synthesis error)• Accepts crystal (8–48 MHz), single-ended (8–250 MHz) or differential (8–700 MHz) reference• Generates up to 12 outputs:– 8 differential pairs: LVDS / LVPECL / CML / HCSL, 25 MHz–700 MHz– 12 LVCMOS: 3 MHz–250 MHz (one output down to 1 kHz)• RMS phase jitter: 1 ps max (12 kHz–20 MHz offset, 156.25 MHz output)• Skew ≤ 100 ps between differential outputs in same bank• Spread-spectrum: 0.1 %–5 % down/center, 30–60 kHz modulation (digital Frac-N)• VCXO function on PLL1: ±120 ppm pull-range, 0.23 ppm/step via analog VIN pin• Zero-delay-buffer (ZDB) & non-zero-delay-buffer (NZDB) modes supported• Hitless switching / frequency-select via 3 hardware pins (FS0-FS2) or I²C
3. Default Factory Image (025)• Pin-controlled device (I²C still available for field tuning)• Pre-defined 25 MHz crystal input → common networking frequencies (100 MHz, 125 MHz, 156.25 MHz, 74.25 MHz video, 24 MHz USB, 32.768 kHz RTC, etc.)• Exact table shipped with device; user can overwrite into NV memory if required
4. Electrical Ratings• Supply: 1.8 V, 2.5 V or 3.3 V core (VDD) and independent bank supplies (VDDIO_Dx / VDDIO_Sx)• Max current (typ):– Core + 4 PLLs active ≈ 38 mA @ 3.3 V– Per LVDS pair 13.25 mA (100 Ω load)– Per HCSL pair 18 mA (50 Ω to GND)– Per CMOS 6 mA (10 pF, 33 MHz)• Power-down mode: < 2 mA total• Lock time: 4 ms (XO mode) / 10 ms (PLL ±1 ppm)• Absolute max: VDDx –0.5 V … 4.6 V, VI –0.5 V … VDD+0.4 V• ESD: HBM 2 kV, CDM 500 V, Latch-up 140 mA
5. AC / Timing Specifications (industrial temp)• Additive RMS jitter: 0.7 ps typ (156.25 MHz, 12 k–20 MHz)• Period jitter (pk-pk): 50 ps (100 MHz, 10 k cycles)• Cycle-to-cycle: 50 ps pk (same conditions)• Duty cycle: 45 %–55 % (≥200 MHz), 40 %–60 % (< 200 MHz)• Rise/fall times: 450 ps max (diff, 622 MHz)• Frequency-switching time: 500 µs (MUX change) / 1 ms (PLL divider change)
6. Pin Summary (48-QFN)• Clock I/O: 8 diff-pairs (OUT11P/N … OUT24P/N) + 4 single-ended (OUT15/16/25/26)• Reference: XIN/XOUT (crystal), IN1P/N, IN2P/N (diff/LVCMOS)• Control: FS0-2, XRES (reset), VIN (VCXO analog)• Serial: SCLK, SDAT (I²C 400 kHz, 7-bit addr 0x69 default)• Power: VDD (core), VDDIO_D1/2, VDDIO_S1/2, GND (exposed pad), VCCD (1.8 V bypass)
7. Thermal & Package• θJA = 15.6 °C/W (JEDEC 51, still air)• θJC = 2.2 °C/W• Moisture sensitivity MSL-3, peak reflow 260 °C, 30 s above 255 °C• Weight: 95 mg typ
8. Compliance & Support• PCIe 1/2/3 common-clock & separate-ref, SATA 2.0, USB 2.0/3.0, 1/10-GbE compliant• Industrial temp qualified, RoHS/REACH lead-free, halogen-free mould compound• Configuration support: ClockWizard 2.1 GUI, In-system programming via I²C• Field re-programming: 100 k NV cycles, 10-year data retention
9. Typical Applications• Networking line-cards (100 M/1 G/10 G)• PCIe add-in cards, NVMe SSDs• Video broadcast equipment (HD-SDI, 74.25 MHz)• Industrial PCs, FPGA clock trees• USB 3.0 hubs, SATA controllers
10. Ordering Alternatives• Field-programmable blank device: CY27410FLTXI (user programs via I²C)• Other factory images: CY27410LTXI-xxx (xxx = customer-specific code)• Tape-and-reel: append “T” to part number