SK hynix H5AG36EXNDX017N 8Gb DDR4 SDRAM Datasheet Summary

1. Basic Device Information

• Manufacturer: SK hynix
• Part Number: H5AG36EXNDX017N
• Device Type: 8Gb CMOS Double Data Rate IV (DDR4) Synchronous DRAM
• Revision: Rev. 1.0 / Dec. 2021
• Compliance: Lead-Free, Halogen-Free, RoHS Compliant
• Application: Main memory for high-density, high-bandwidth systems

2. Key Features

• Supply Voltage: VDD = VDDQ = 1.2V ± 0.06V; VPP = 2.5V (2.375V min, 2.75V max)
• Fully differential clock inputs (CK_t / CK_c) & differential data strobe (DQS_t / DQS_c)
• On-chip DLL for DQ/DQS/CK alignment
• 8-bit prefetch architecture
• Programmable burst length: 4/8 (sequential & interleave mode)
• 16 banks with bank grouping
• Dynamic On Die Termination (ODT): RTT_PARK, RTT_NOM
• Asynchronous RESET pin supported
• ZQ calibration & Write Levelization
• TDQS (x8 only), DBI (Data Bus Inversion, x8 only)
• Write CRC & CA Parity supported
• TCAR, LP ASR, Fine Granularity Refresh supported
• Geardown Mode (1/2, 1/4 rate) supported
• Per DRAM Addressability supported

3. Configuration & Package

• Organization: 512M x 16
• Package: 96-ball FBGA
• Serial Code (12–14 digits): 017 (8Gb, 96-ball, 1-die)
• Temperature Grade: Commercial (0 °C ~ 85 °C)

4. Speed Grade & Timing Parameters

• Speed Bin: DDR4–2133 (TF)
• Data Rate: 2133 MT/s
• tCK: 0.937 ns
• CAS Latency: 15
• Timing: CL–tRCD–tRP = 15–15–15
• tRAS: 33 ns
• tRC: 47.06 ns (46.50 ns optional)
• Supported downgrade CL: 11, 13, 15, 17, 19, 21

5. Refresh Specifications (8Gb)

• Base refresh interval (tREFI_base): 7.8 μs
• 0 °C ~ 85 °C: tREFI1 = 7.8 μs; tRFC1(min) = 350 ns
• 85 °C ~ 95 °C: tREFI1 = 3.9 μs
• 2X mode: tREFI2 = 3.9 μs / 1.95 μs; tRFC2(min) = 260 ns
• 4X mode: tREFI4 = 1.95 μs / 0.975 μs; tRFC4(min) = 160 ns

6. Operating Temperature Range

• Normal (Commercial): 0 °C ~ 85 °C (full spec guaranteed)
• Extended: 85 °C ~ 95 °C (refresh doubled to 3.9 μs)
• Storage Temperature: -55 °C ~ +100 °C

7. Absolute Maximum Ratings

• VDD / VDDQ: -0.3 V ~ 1.5 V
• VPP: -0.3 V ~ 3.0 V
• VIN / VOUT: -0.3 V ~ 1.5 V
• VDD and VDDQ must be within 300 mV at all times
• VPP ≥ VDD / VDDQ at all times

8. Recommended DC Operating Conditions

表格

9. Bank & Address Mapping (512M x16)

• Number of Bank Groups: 2
• Bank Group Address: BG0 only
• Bank Address per Group: BA0 ~ BA1
• Row Address: A0 ~ A15
• Column Address: A0 ~ A9
• Page Size: 2 KB

10. Power Consumption (IDD / IPP)

• Typical values at DDR4–2133 (x16):

11. Input/Output Capacitance

• CIO (I/O capacitance): 0.55 pF (min) ~ 1.00 pF (max)
• CCK (Clock input capacitance): 0.2 pF ~ 0.7 pF
• CI (CTRL/ADD/CMD input capacitance): 0.2 pF ~ 0.6 pF
• CZQ (ZQ pin): 2.3 pF
• CALERT (ALERT_n pin): 0.5 pF ~ 1.5 pF

12. Package Electrical Specifications (x16)

• ZIO (I/O impedance): 45 Ω ~ 85 Ω
• TdIO (Package delay): 14 ps ~ 45 ps
• LIO (Package inductance): 3.4 nH max
• CIO (Package capacitance): 0.82 pF max
• ZI_CTRL / ZI_ADD_CMD: 50 Ω ~ 90 Ω
• ZCK: 50 Ω ~ 90 Ω

13. Package Dimensions

• Package Type: 96-ball FBGA
• Pitch: 0.450 ± 0.050 mm
• Outline: 7.500 mm × 7.500 mm
• Post-reflow thickness: 0.500 ± 0.050 mm