PI6CDBL401BZHIE - 4-Output Low Power PCIe Gen1-2-3 Buffer

Comprehensive Technical Information

1. Product Overview

1.1 Basic Information

• Base Model: PI6CDBL401B
• Full Ordering Code: PI6CDBL401BZHIEX (Tape & Reel)
• Manufacturer: Diodes Incorporated
• Package Type: 32-contact Thin Quad Flat No-Lead (TQFN), Lead-free
• Product Line: Pericom Interface Solutions

1.2 Key Features

• 4x 100MHz Low Power HCSL or LVDS Compatible Outputs
• PCIe 3.0, 2.0, and 1.0 Compliant
• Programmable Output Amplitude and Slew Rate
• Integrated Output Terminations (Zo = 100Ω)
• Flexible Supply Voltages:Core Supply (VDDA/VDDR): 3.3V ±10%Output Supply (VDDO): 1.8V, 2.5V, or 3.3V ±10%
• Industrial Temperature Range: -40°C to +85°C
• Independent Output Enables for each differential pair
• SMBus Programmability with 3 selectable addresses
• Three Operating Modes: High Bandwidth PLL, Low Bandwidth PLL, and Bypass Mode

1.3 Applications

• PCIe 3.0/2.0/1.0 Clock Distribution
• Server and Storage Systems
• Networking Equipment
• Data Center Infrastructure

2. Pin Configuration and Description

2.1 Pin Diagram (32-TQFN)

32  31  30  29  28  27  26  25
 ┌─────────────────────────────┐
 │  ████████████████████████  │
1│  ██  PI6CDBL401B        ██  │24
 │  ██                     ██  │
 │  ██                     ██  │
9│  ██                     ██  │16
 │  ████████████████████████  │
 └─────────────────────────────┘
  8   7   6   5   4   3   2   1
  

2.2 Detailed Pin Descriptions

3. Functional Description

3.1 Operating Modes

The device supports three operating modes selected by the HIBW_BYPM_LOBW# pin (Pin 1):

3.2 Power Management

Controlled by CKPWRGD_PD# pin (Pin 32) and individual OE# pins:

3.3 SMBus Address Selection

The SADR_tri pin (Pin 31) selects the SMBus address on first assertion of CKPWRGD_PD#:

TableCopy

4. Electrical Characteristics

4.1 Absolute Maximum Ratings

• Supply Voltage to Ground Potential: 4.6V
• All Inputs and Outputs: -0.5V to VDD + 0.5V
• Ambient Operating Temperature: -40°C to +85°C
• Storage Temperature: -65°C to +150°C
• Junction Temperature: 125°C
• Soldering Temperature: 260°C
• ESD Protection (Input): 2000V (HBM)

4.2 Clock Input Parameters (Differential)

4.3 Supply Voltage Specifications

4.4 Low Power HCSL Output Characteristics

4.5 Jitter and Timing Performance

4.6 Phase Jitter Performance (Critical for PCIe Compliance)

4.7 Current Consumption

5. SMBus Interface and Register Map

5.1 SMBus Protocol

• Device Type: Slave-only device
• Supported Protocols: Block Read and Block Write
• Addressing: Single 7-bit address with R/W bit
• Register Access: Indexed block transfers with register offset

5.2 Key Registers

Register 0: Output Enable Control

Register 1: PLL Mode and Amplitude Control

Register 2: Slew Rate Control

Register 5: Revision and Vendor ID

Register 6: Device Type and ID

6. Application Information

6.1 Driving LVDS Inputs

For interfacing with LVDS receivers:

6.2 Recommended Test Load

• Differential Output: 100Ω differential termination
• Trace Length: 5 inches typical
• Capacitive Load: 2pF per side

7. Thermal and Package Information

7.1 Thermal Characteristics

7.2 Package Dimensions (TQFN-32)

• Package Code: ZH32
• Body Size: 5mm × 5mm (typical)
• Terminal Pitch: 0.5mm
• Exposed Pad: For thermal dissipation
• Coplanarity: Applies to exposed pad and terminals
• Standard: JEDEC MO-220

8. Ordering Information

• E suffix = Pb-free and Green
• X suffix = Tape/Reel packaging

9. Compliance and Certifications

9.1 PCIe Compliance

• PCIe 1.0: Meets 86ps peak-to-peak phase jitter limit
• PCIe 2.0: Meets 3ps/3.1ps RMS jitter limits (Low/High band)
• PCIe 3.0: Meets 1ps RMS phase jitter limit (with CDR = 10MHz)

9.2 Other Standards

• SGMII: Compatible with 125MHz SGMII jitter requirements
• Environmental: Pb-free, RoHS compliant, Green package

10. Design Considerations

10.1 Power Supply Requirements

• Analog Power (VDDA3.3, VDDR3.3): Must be filtered and treated as clean analog rails
• Digital Power (VDDDIG3.3): Can be "dirty" digital power
• Output Power (VDDO1.8): Can be 1.8V, 2.5V, or 3.3V based on system requirements
• Ground Separation: GNDA (PLL) and GNDR (receiver) should have low-impedance return paths

10.2 Input Clock Requirements

• Frequency: 100MHz nominal (95-105MHz PLL mode, up to 400MHz bypass)
• Amplitude: 300mV to 1450mV peak-to-peak differential
• Slew Rate: Minimum 0.4V/ns differential
• Single-Ended Option: Can drive CLK_IN single-ended by biasing CLK_IN# to VBIAS

10.3 Power Sequencing

1. Apply power to all VDD rails
2. Wait for power stabilization (tSTAB = 0.6-1ms)
3. Assert CKPWRGD_PD# high to start device
4. Ensure input clock is stable before assertion

11. Important Notices

11.1 Warranty Disclaimer

DIODES INCORPORATED makes no warranty of any kind, express or implied, regarding this document or products. Information is subject to change without notice.

11.2 Life Support Policy

Not authorized for use as critical components in life support devices or systems without express written approval from the Chief Executive Officer of Diodes Incorporated.

11.3 Unauthorized Applications

Customers using products in unintended applications must indemnify Diodes Incorporated against all claims, damages, and expenses.

11.4 Intellectual Property

Diodes Incorporated does not convey any license under its patent or trademark rights.